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Deserializer
SV51007
2014.01.10
? The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN .
Figure 6-21: Data Realignment Timing
This figure shows receiver output ( RX_OUT ) after one bit slip pulse with the deserialization factor set to 4 .
rx_inclock
rx_in
3
2
1
0
3
2
1
0
3
2
1
0
rx_outclock
rx_channel_data_align
rx_out
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The
programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor.
Set the programmable bit rollover point equal to, or greater than, the deserialization factor — allowing enough
depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point
using the MegaWizard Plug-In Manager. An optional status port, RX_CDA_MAX , is available to the FPGA
fabric from each channel to indicate the reaching of the preset rollover point.
Figure 6-22: Receiver Data Realignment Rollover
This figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses for
one rx_outclock cycle to indicate that rollover has occurred.
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
Deserializer
You can statically set the deserialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 by using the Quartus II
software. You can bypass the deserializer in the Quartus II MegaWizard Plug-In Manager to support DDR
(x2) or SDR (x1) operations, as shown in the following figure.
Altera Corporation
High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
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